The present invention relates to a semiconductor memory device which includes address generation means therein, and more particularly to a FIFO memory (first-in first-out memory) which temporarily stores data in first-in first-out fashion. It consists of techniques which are effective when applied to, for example, a communication controlling LSI and a communication control system.
In the case where data items are transferred among a plurality of devices or function modules which have different rates of data processing or data transferring, FIFO memories or the like can be utilized as buffer memories for the purpose of absorbing such differences in the capabilities or the rates. In, for example, a communication controlling LSI, a transmitting FIFO memory and a receiving FIFO memory are arranged between a line control unit, which transmits and receives data to and from communication lines, and a bus interface unit which is connected with host equipment. The receiving FIFO memory stores the received data items of the line control unit in succession, and the host equipment reads out the stored data items through the bus interface unit in succession so as to subject them to data transfer or data processing. The transmitting FIFO memory stores transmission data items supplied from the host equipment thereto through the bus interface unit, in succession, and the line control unit reads out the stored data items in succession so as to subject them to transmission.
Regarding the receiving FIFO memory or the transmitting FIFO memory, it is necessary to control the number of data items to-be-stored at will and, further, to inform the host equipment of the number of stored data items in real time. The number of data items should be controlled to reduce the overhead time for the data transfer and prevent the overrun of reception data items. A technique for counting the number of stored data items of the FIFO memory employs a dedicated counter which is incremented each time the FIFO memory is instructed to perform a write operation and which is decremented each time it is instructed to perform a read operation, as disclosed in the official gazette of Japanese Patent Application Laid-open No. 225050/1987.
Further, frames or characters in the transmission/reception of data are usually transferred with 8 bits as the minimum unit. The transmitting FIFO memory or receiving FIFO memory in the prior art is therefore adapted to transfer data in 8-bit units between itself and the line control unit. Accordingly, the transmitting or receiving FIFO memory and the bus interface unit have been connected by only one bus of 8 bits. An example of literature containing a bus structure of the FIFO memory of this type is Intel Inc., U.S.: 82586 (LAN Components Users Manual 2. 13, issued in March 1984).
However, when a single dedicated counter is incremented for every writing operation and decremented for every reading operation, a problem arises if the writing and the reading simultaneously occur. This simultaneous occurrence of reading and writing makes it difficult to obtain an accurate count of the number of stored data items.
Further, the inventor has conducted a study concerning the technique for requesting the host equipment to transfer transmission data on the basis of 1) the number of stored transmission data items which have been transferred from the host equipment to the transmitting FIFO memory and 2) the number of stored transmissions data items which remain in this FIFO memory. The prior art only requests data transfer in accordance with the remaining number of the stored data items, and not in accordance with the number of the data items which are transferred from the host equipment to the transmitting FIFO memory. In the case where a large number of transmitting FIFO memories are disposed in correspondence with the respective channels of the line control unit which supports a large number of channels, many of the transmitting FIFO memories request the host equipment to transfer data in some operations. The prior art does not allow the negate conditions of the transfer requests for the transmitting FIFO memories to be set at will. Thus, the bus might be occupied due to the data transfers to the transmitting FIFO memories, and any other necessary processing by the host equipment might be hampered.
In addition, in the case where the bus interface unit in the communication control unit can be connected with the host equipment through a bus having a bit configuration of 16 bits, for example, data items are transferred in 16-bit units between the host equipment and the bus interface unit. When the transmitting FIFO memory or receiving FIFO memory and the bus interface unit are connected by an 8-bit bus as in the prior art, data items which exceed 8-bits must be divided. Each portion must then be transferred between the transmitting or receiving FIFO memory and the bus interface unit. This lowers the efficiency of the data transfer between the FIFO memory and the host equipment.
Meanwhile, the FIFO memory comprises address counters, such as a read counter and a write counter, in order to store data in first-in first-out fashion. The addresses of accesses to memory cell arrays are designated by the read and write counters. The values of the read and write counters are held in agreement under the empty state while no data item is stored in the memory cell arrays. The value of the write counter is incremented each time a data writing operation is instructed, while the value of the read counter is incremented each time a data reading operation is instructed. An example of literature containing such a FIFO memory is "NIKKEI ELECTRONICS" issued by Nikkei McGraw-Hill Kabushiki-Kaisha, No. 423 (dated Jun. 15, 1987), pp. 181-188. In the prior-art FIFO memory, however, the sequences of reading and writing data items are uniquely determined by the built-in address counters, such as read and write counters. Thus, random accesses to memory cells, which might be required, cannot be accomplished. Consequently, the prior art encompasses the following drawbacks: 1) when a data item that needs to be checked is not the first stored data item in the FIFO memory, all data items stored ahead of the desired data item must be output in succession; 2) in order to clear unnecessary data items which have appeared in the FIFO memory due to an error or the like in a system operation, all the unnecessary data items must be read out in succession in order to update the value of the read counter; and, 3) time is expended on the data checking operation or the data clearing operation. Thus, the real time processing of data is impeded.